Semiconductor device including power MOSFET and peripheral device and method for manufacturing the same

ABSTRACT

First and second trenches are formed on an n +  type substrate at a power MOSFET formation region and a peripheral device formation region, respectively. An n −  type epitaxial film, a p type epitaxial film, and an n +  type epitaxial film are deposited on the substrate and in the trenches, and then flattening is performed. As a result, an n −  type region is provided in the second trench of the peripheral device formation region. Then, a p type well layer is formed in the n −  type region by ion-implantation. Accordingly, a power MOSFET and a peripheral device can been formed at the power MOSFET formation region and the peripheral device formation region easily.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of JapanesePatent Applications No. 2000-79344 filed on Mar. 16, 2000, and No.2000-79346 filed on Mar. 16, 2000, the contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to a semiconductor device including apower MOSFET and peripheral devices, and a method for manufacturing thesame.

[0004] 2. Description of Related Art

[0005] The Applicant proposes, in Japanese Patent nonpublishedapplication No. 2000-10350, a semiconductor device (MOSFET) capable ofreducing an ON resistance by setting a channel width parallel to asubstrate depth direction. The MOSFET adopts an n⁺ type substrate thatfunctions as a drain region. Meanwhile, it is required to formperipheral devices such as a CMOS for monitoring a temperature, a diode,and a MOSFET for controlling the power MOSFET on one chip together withthe power MOSFET described above. That is, these peripheral devices andthe power MOSFET are required to be formed on an identical substrate.

[0006] Therefore, when the n⁺ type substrate is used for the powerMOSFET, the peripheral devices must be formed in the n⁺ type substrateother than the region where the power MOSFET is formed. However, thismakes it difficult to control concentrations of diffusion layers for theperipheral devices. Further, the peripheral devices must be isolatedfrom the drain region (the n⁺ type substrate 1) of the power MOSFET.

SUMMARY OF THE INVENTION

[0007] The present invention has been made in view of the aboveproblems. An object of the present invention is to make it easier tocontrol a concentration of a diffusion layer for a peripheral devicethat is formed together with a power MOSFET in an identical substrate.Another object of the present invention is to provide a semiconductordevice including a power MOSFET and a peripheral device, which can beformed in an identical substrate by a simplified manufacturing method.

[0008] According to a first of the invention, a first conductivity typehigh-concentration semiconductor substrate has a first trench at a powerMOSFET formation region for forming a power MOSFET, and a second trenchat a peripheral device formation region for forming a peripheral device.A second conductivity type well layer is disposed in the second trench.

[0009] According to a second aspect of the invention, a firstconductivity type high-concentration semiconductor substrate has asecond conductivity type semiconductor layer thereon. A peripheraldevice is formed in the semiconductor layer except a region where apower MOSFET is formed. In these semiconductor devices, a concentrationof a diffusion resistance of the peripheral device can be controlledeasily despite the high-concentration substrate including the powerMOSFET and the peripheral device together.

[0010] According to a third aspect of the invention, a peripheral devicehas a similar structure as that of a power MOSFET. Specifically, theperipheral device is a first conductivity type channel MOSFET composedof a well layer of a first conductivity type extending in asemiconductor substrate, a base region of a second conductivity typeextending in the well layer, a semiconductor region of the firstconductivity type extending in the base region, a trench dividing thesemiconductor region into a source region and a drain region, a gateinsulating film provided on an inner wall of the trench, and a gateelectrode provided on a surface of the gate insulating film and fillingthe trench.

[0011] In this case, the peripheral device can be manufactured at thesame manufacturing steps as those for the power MOSFET simultaneously,resulting in a simplified manufacturing method. The peripheral device isnot limited to the first conductivity type channel MOSFET as mentionedabove, but may be a second conductivity type channel MOSFET. Otherwise,the peripheral device can include both the first conductivity typechannel MOSFET and the second conductivity type channel MOSFET, i.e.,n-channel MOSFET (nMOS) and p-channel MOSFET (pMOS).

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other objects and features of the present invention will becomemore readily apparent from a better understanding of the preferredembodiments described below with reference to the following drawings, inwhich;

[0013]FIGS. 1A to 1E are cross-sectional views showing steps formanufacturing a semiconductor device according to a first embodiment ofthe invention;

[0014]FIGS. 2A to 2E are cross-sectional views showing steps followingthe steps shown in FIGS. 1A to 1E;

[0015]FIG. 3 is a cross-sectional view showing a semiconductor device ina second embodiment;

[0016]FIG. 4 is a cross-sectional view showing a semiconductor device ina third embodiment;

[0017]FIG. 5 is a cross-sectional view showing a semiconductor device ina fourth embodiment;

[0018]FIGS. 6A to 6C are cross-sectional views showing steps formanufacturing a semiconductor device in a fifth embodiment;

[0019]FIGS. 7A to 7C are cross-sectional views showing steps formanufacturing a semiconductor device in a sixth embodiment;

[0020]FIG. 8 is a cross-sectional view showing a power MOSFET in thefirst embodiment, which is substantially the same as that proposed bythe applicant in Japanese Patent non-published application No.2000-10350;

[0021]FIG. 9 is a diagram schematically showing a layout of asemiconductor device according to a seventh embodiment of the invention;

[0022]FIG. 10 is a perspective cross-sectional view showing thesemiconductor device along lines X-O-X in FIG. 9;

[0023]FIG. 11 is a schematic view for explaining an operation of ann-channel MOSFET as a peripheral device in the seventh embodiment;

[0024]FIG. 12 is a perspective cross-sectional view showing a peripheraldevice according to an eighth embodiment of the invention;

[0025]FIG. 13 is a schematic view for explaining an operation of ap-channel MOSFET shown in FIG. 12;

[0026]FIG. 14 is a schematic view showing a structure of a p-channelMOSFET as a modified embodiment;

[0027]FIG. 15 is a schematic view showing a structure of a p-channelMOSFET as another modified embodiment; and

[0028]FIG. 16 is a perspective cross-sectional view showing a powerMOSFET in the seventh and eighth embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] First, a structure of a power MOSFET is explained with referenceto FIG. 8. As shown in FIG. 8, the power MOSFET is composed of an n⁺type substrate 1 having a main surface 1 a and a back surface 1 bopposed to the main surface 1 a. The thickness direction of the n⁺ typesubstrate 1 corresponds to arrowed direction X, and arrowed directions Yand Z in the figure are parallel to the main and back surfaces 1 a, 1 bof the n⁺ type substrate 1. The directions X, Y, and Z are perpendicularto one another.

[0030] An n⁻ type drift region 1 c is formed in the n⁺ type substrate 1to have a specific depth from the main surface 1 a, and a p type baseregion 2 is formed in the n⁻ type drift region 1 c to have a specificdepth from the main surface 1 a. The depth of the p type base region 2is about 1 to 100 μm. An n⁺ type source region 3 is further formed inthe p type base region 2 to have a junction depth shallower than that ofthe p type base region 2. The depth of the n⁺ type source region 3 isabout 1 to 100 μm, but is somewhat shallower than the p type base region2. The n⁺ type substrate 1 has an impurity concentration approximatelyequal to that of the n⁺ type source region 3, and constitutes a drainregion.

[0031] Trenches 5 are etched from the main surface 1 a of the n⁺ typesubstrate 1 perpendicularly, i.e., in a direction approximately parallelto the direction X. The trenches 5 penetrate the n⁺ type source region 3and the p type base region 2 in both the direction Y parallel to themain surface 1 a and the direction X parallel to the depth direction ofthe trenches 5. A gate oxide film 6 is formed on the inner walls of thetrenches 5, and the insides of the trenches 5 are filled with a gateelectrode 7 with the gate oxide film 6 interposed therebetween.

[0032] (First Embodiment)

[0033] Next, a method for manufacturing a semiconductor device, in whicha peripheral device is formed together with the power MOSFET shown inFIG. 8 on the identical n⁺ type substrate 1, is explained with referenceto FIGS. 1A to 1E, and FIGS. 2A to 2E as a first embodiment of theinvention.

[0034] [Step shown in FIG. 1A]

[0035] First, the n⁺ type substrate 1 having the main surface 1 a andthe back surface 1 b is prepared. A (110) Si substrate having animpurity concentration of about 1×10¹⁹cm⁻³ is used as the n⁺ typesubstrate 1 in this embodiment. Then, an oxide film 21 with a thicknessof about 1 μm is disposed on the main surface 1 a of the n⁺ typesubstrate 1, as a mask material, and resist 20 a is disposed on theoxide film 21. After that, the resist 20 a is opened, in a photo step,above a region where the n⁻ type drift region 1 c is to be formed (i.e.,at a drift formation region).

[0036] [Step shown in FIG. 1B]

[0037] The oxide film 21 is etched using the resist 20 a as a mask, andthe oxide film 21 is opened at the drift formation region. Successively,a trench (first trench) 8 is formed by performing dry etching to the n⁺type substrate 1 at the drift formation region, using the oxide film 21as a mask.

[0038] Instead of the dry etching, the trench 8 may be formed byanisotropic wet etching in this step using, for example, a potassiumhydroxide solution or a tetramethylammonium hydroxide solution. When oneof these etching solutions is used, the aspect ratio of the trench 8 canbe increased by using the (110) Si substrate as the n⁺ type substrate 1,and by so designing that the sidewalls of the trench 8 are defined by a(1{overscore (1)}1) plane and a ({overscore (1)}1{overscore (1)}) plane,or by a ({overscore (1)}11) plane and a (1{overscore (11)}) plane. Thisis because the etching rate is small with respect to the (1{overscore(1)}1), ({overscore (1)}1{overscore (1)}), ({overscore (1)}11), and(1{overscore (11)}) planes that are perpendicular to the (110) plane.

[0039] [Step shown in FIG. 1C]

[0040] A heat treatment is performed. Accordingly, the inner walls ofthe trench 8 are thermally oxidized so that an oxide film is formed onthe sidewalls of the trench 8 with a thickness of about 500 Å, as a partof the oxide film 21. At that time, the corner portions formed at thetrench bottom face and the trench sidewall are rounded by oxidation.

[0041] [Step shown in FIG. 1D]

[0042] Resist 20 b is disposed on the oxide film 21, and is opened at aregion where the peripheral device is to be formed (i.e., at aperipheral device formation region).

[0043] [Step shown in FIG. 1E]

[0044] The oxide film 21 is etched using the resist 20 b as a mask, andaccordingly is opened at the peripheral device formation region.Successively, a trench (second trench) 9 is formed at the peripheraldevice formation region by performing dry etching using the oxide film21 as a mask. This trench formation may be performed by anisotropic wetetching as in the step shown in FIG. 1B to achieve the same advantagesas described above.

[0045] [Step shown in FIG. 2A]

[0046] The oxide film 21 is further etched using hydrogen fluoride (HF)so that a part of the film 21 having a thickness of about 500 Å isremoved. As a result, the oxide film 21 remains only on the main surface1 a of the n⁺ type substrate 1, and the n⁺ type substrate 1 is exposedon the sidewalls of the trenches 8, 9.

[0047] [Step shown in FIG. 2B]

[0048] An n⁻ type epitaxial film (first semiconductor film) 22, an ptype epitaxial film (second semiconductor film) 23, and an n⁺ typeepitaxial film (third semiconductor film) 24 are grown in sequence onthe main surface 1 a as well as on the sidewalls of the trenches 8, 9.At that time, the thickness of the n⁻ type epitaxial film 22 iscontrolled to be larger than depth d1 of the trench 9 so that the p typeepitaxial film 23 does not get into the trench 9. Incidentally, becausethe corner portions of the trench 8 are rounded, the corner portions ofthe n⁻ type epitaxial film 22 and the p type epitaxial film 23 are alsorounded above the trench 8. This is effective to relax electric fieldconcentrations thereon.

[0049] [step shown in FIG. 2C]

[0050] Etching-back is performed to the n⁻ type epitaxial film 22, the ptype epitaxial film 23, and the n⁺ type epitaxial film 24, using theoxide film 21 as an etching stopper. As a result, the regions where thepower MOSFET and the peripheral device are to be formed are flattened.At the region where the power MOSFET is to be formed (i.e., at the powerMOSFET formation region), the n⁻ type drift region 1 c is made up of then⁻ type epitaxial film 22, the p type base region 2 is made up of the ptype epitaxial film 23, and the n⁺ type source region 3 is made up ofthe n⁺ type epitaxial film 24. On the other hand, at the region wherethe peripheral device is to be formed, an n⁻ type region (semiconductorlayer) 11 is made up of the n⁻ type epitaxial film 22. Incidentally,although the case of performing the etch-back is explained here, theflattening may be performed by polishing using the oxide film 21 as afilm for detecting an end point, or by wet etching and finishingpolishing.

[0051] [Step shown in FIG. 2D]

[0052] After the surface portions of the n⁻ type drift region 1 c, the ptype base region 2, the n⁺ type source region 3, and the n⁻ type region11 are oxidized sacrificially, the sacrificially oxidized portions areremoved by etching. Accordingly, the main surface 1 a of the n⁺ typesubstrate are flattened almost at an entire region thereof.

[0053] The oxide film 21 on the main surface 1 a of the n⁺ typesubstrate 1 may be removed before the growths of the epitaxial films. Inthis case, substantially the same structure as described above can beattained by controlling polishing rates of the epitaxial films 22, 23and 24 or by measuring the thickness of the substrate at the flatteningstep, without performing the sacrificial oxidation treatment.

[0054] [Step shown in FIG. 2E]

[0055] Then, a p type well layer 12 is formed in a surface portion ofthe n type region 11 by ion-implantation or the like. Accordingly, the ptype well layer 12 is formed at a position separated from the n⁺ typesubstrate 1. In this p type well layer 12, the peripheral device such asa CMOS or a diode is formed.

[0056] According to the structure described above, the n⁻ type region 11having an impurity concentration lower than that of the n⁺ typesubstrate 1 extends between the p type well layer 12 and the highconcentration n⁺ type substrate 1. Because of this, a depletion layerformed between the p type well layer 12 and the n⁻ type region 11 caneasily extends to the side of the n⁻ type region 11, so that thewithstand voltage of the p type well layer 12 can be improved.

[0057] After that, although steps are not shown specifically, as shownin FIG. 8, the trenches 5 are etched from the main surface 1 a of the n⁺type substrate 1 vertically, the gate oxide film 6 is formed on thesurfaces of the trenches 5, and the gate electrode 7 is formed on thegate oxide film 6. In consequence, the power MOSFET shown in FIG. 8 iscompleted.

[0058] Thus, according to the present embodiment, the trench 8 forforming the power MOSFET and the trench 9 for forming the peripheraldevice are formed on the same substrate 1, and the p type well layer 12of a conductivity type inverse to that of the n⁺ type substrate 1 isformed in the trench 9. Therefore, a concentration of a diffusionresistance of the peripheral device can be controlled easily, and thereis no need to isolate the peripheral device formation region from drainof the power MOSFET specially.

[0059] Although it is explained that the trench 8 for forming the powerMOSFET and the trench 9 for forming the peripheral device are formed inthe present embodiment, the present embodiment is applicable to a casewhere more than two trenches are formed on the n⁺ type substrate 1. Thesame advantages described above can be attained by forming at least twotrenches having different sizes on the n⁺ type substrate 1 and byforming, in one of the trenches for forming the peripheral device, asemiconductor layer (the p type well layer 12 in this embodiment) of aconductivity type different from that of the substrate 1.

[0060] (Second Embodiment)

[0061]FIG. 3 shows a cross-sectional structure of a semiconductor deviceto which a second embodiment of the invention is applied. In the firstembodiment, as shown in FIGS. 1A to 1E, the trench 8 and the trench 9are formed separately from each other. As opposed to this, in the secondembodiment, at the step shown in FIG. 1B, the oxide film 21 is openednot only at the power MOSFET formation region but also at the peripheraldevice formation region, and the trenches 8 and 9 are formed at the sametime. In this case, as shown in FIG. 3, the depth of the trench 9 isequal to that of the trench 8. Therefore, the width of the trench 9 isset to be less than twice (L1×2) as large as thickness L1 of the n⁻ typeepitaxial film 22 so as to prevent the p type epitaxial film 23 fromgetting into the trench 9.

[0062] Thus, when the trench 8 and the trench 9 are formedsimultaneously, not only the formation step of the trenches 8, 9 butalso the manufacturing process of the semiconductor device can besimplified. Further, because the p type well layer 12 and the p typebase region 2 can be formed with different concentrations from eachother, the concentration of the p type well layer 12 can be controlleddesirably.

[0063] (Third Embodiment)

[0064]FIG. 4 shows a cross-sectional structure of a semiconductor deviceto which a third embodiment of the invention is applied. In the firstembodiment, as shown in FIG. 2B, only the n⁻ type epitaxial film 22 isdisposed in the trench 9. To the contrary, in the third embodiment, then⁻ type epitaxial film 22 and the p type epitaxial film 23 are disposedin the trench 9. In the semiconductor device having the structure asdescribed above, in the step shown in FIG. 1E, the trench 9 is formedwith a depth d2 that allows both the n⁻ type epitaxial film 22 and the ptype epitaxial film 23 to be disposed in the trench 9. The semiconductordevice in this embodiment also can be manufactured by the samemanufacturing method as that of the first embodiment.

[0065] In the third embodiment, the p type well region 12 is formed fromthe p type epitaxial film 23. Therefore, unlike the first embodiment,ion-implantation needs not be performed to form the p type well region12. This embodiment is especially preferable in the case where the ptype base region 2 and the p type well region 12 may have the sameimpurity concentration as each other.

[0066] (Fourth Embodiment)

[0067]FIG. 5 shows a cross-sectional structure of a semiconductor deviceto which a fourth embodiment of the invention is applied. The presentembodiment is a combination of the second and third embodiments. Thatis, the trenches 8, 9 are formed simultaneously, and both the n⁻ typeepitaxial film 22 and the p type epitaxial film 23 are disposed in thetrench 9. Accordingly, the formation step of the trenches 8, 9 issimplified, and there is no need to perform ion-implantation for formingthe p type well region 12.

[0068] The semiconductor device having the abovementioned structure canbe manufactured by the same method as that of the first embodiment whenthe width of the trench 9 is set to be twice or less than twice (L2×2)as large as thickness L2 that is the sum of the thickness of the n⁻ typeepitaxial film 22 and the thickness of the p type epitaxial film 23. Inthis case, however, it is necessary that the width of the trench 9 ismore than twice (L1×2) as large as the thickness L1 of the n⁻ typeepitaxial film 22, unlike the second embodiment.

[0069] (Fifth Embodiment)

[0070]FIGS. 6A to 6B show a manufacturing method of a semiconductordevice in a stepwise manner according to a fifth embodiment of theinvention. Hereinafter, the manufacturing method of the semiconductordevice is explained with reference to the figures.

[0071] [Step shown in FIG. 6A]

[0072] First, an n⁺ type substrate 31 having a main surface 31 a and aback surface 31 b is prepared. In this embodiment, a (110) Si substratehaving an impurity concentration of about 1×10¹⁹ cm⁻³ is used as the n⁺type substrate 31. Then, a p⁻ type epitaxial layer 30 is deposited onthe main surface 31 a of the n⁺ type substrate 31.

[0073] [Step shown in FIG. 6B]

[0074] After a mask having an opening where the n⁻ type drift region 1 cis to be formed is formed in a photo-step, a trench 33 is formed in thep⁻ type epitaxial layer 30 and the n⁺ type substrate 31 by dry etchingusing the mask. Then, the mask is removed.

[0075] Although the trench 33 is formed by dry etching, it may be formedby anisotropic wet etching using a potassium hydroxide solution or atetramethylammonium hydroxide solution. When one of these etchingsolutions is used, an aspect ratio of the trench 33 can be increased byusing the (110) Si substrate as the n⁺ type substrate 31, and by sodesigning that the sidewalls of the trench 33 are defined by a(1{overscore (1)}1) plane and a ({overscore (1)}1{overscore (1)}) plane,or by a ({overscore (1)}11) plane and a (1{overscore (11)}) plane. Thisis because the etching rate is small with respect to the (1{overscore(1)}1), ({overscore (1)}1{overscore (1)}), ({overscore (1)}11), and(1{overscore (11)}) planes that are perpendicular to the (110) plane.

[0076] [Step shown in FIG. 6C]

[0077] Next, an n⁺ type epitaxial film 32 is deposited, so that thesidewalls of the trench 33 are covered with the n⁺ type epitaxial film32. The n⁺ type epitaxial film 32 and the n⁺ type substrate 31 work as adrain (corresponding to the n⁺ type substrate 1 in the first embodiment)of the power MOSFET. Then, substantially the same steps as in the firstembodiment shown in FIG. 2B and following it are performed. Accordingly,the n⁻ type drift region 1 c, the p type base region 2, and the n⁺ typesource region 3 are formed.

[0078] The semiconductor device described above is so constructed thatthe p⁻ type epitaxial layer 30 is disposed at the region where theperipheral device is to be formed (peripheral device formation region).The p⁻ type epitaxial layer 30 therefore corresponds to the p type welllayer 12 in FIG. 1. Because of this, the concentration of the diffusionresistance of the peripheral device can be controlled easily bycontrolling the conditions for depositing the p⁻ type epitaxial layer30. In this semiconductor device, because the peripheral device is notformed on the n⁺ type substrate 31 directly, it is not necessary tospecially isolate the peripheral device formation region from the drainof the power MOSFET.

[0079] Further, because the trench 33 is formed at the region where thepower MOSFET is to be formed (MOSFET formation region) and no trench isformed at the peripheral device formation region, only one mask is usedfor the trench formation. The thickness of the peripheral deviceformation region (here, the p⁻ type epitaxial layer 30) can be setarbitrarily. This means that various kinds of peripheral devices can beformed at that region. Furthermore, it is not necessary to performion-implantation for forming the p type well layer 12 when theconcentration of the p⁻ type epitaxial layer 30 is controlled to be adesirable value.

[0080] Meanwhile, in the present embodiment, the n⁻ type drift region 1c is surrounded with the n⁺ type epitaxial film 32. This is toefficiently form a current path by forming a drain part in that portioncontacting the p⁻ type epitaxial layer 30. Because the thickness of thep⁻ type epitaxial layer 30 is very thin as compared to the depth of thetrench 33 (channel width of the power MOSFET), there is a case where then⁺ type epitaxial film 32 may not be formed.

[0081] (Sixth Embodiment)

[0082]FIGS. 7A to 7C show a manufacturing method of a semiconductordevice in a stepwise manner according to a sixth embodiment of theinvention. Hereinafter, the manufacturing method of the semiconductordevice is explained with reference to the figures.

[0083] [Step shown in FIG. 7A]

[0084] First, an n⁺ type substrate 40 having a main surface 40 a and aback surface 40 b is prepared. A (110) Si substrate having an impurityconcentration of about 1×10¹⁹cm⁻³ is used as the n⁺ type substrate 40 inthis embodiment. Then, a p⁻ type epitaxial layer 42 is deposited on themain surface 40 a of the n⁺ type substrate 40 with an insulating film 41(for example, oxide film) interposed therebetween. Accordingly, an SOIsubstrate composed of the n⁺ type substrate 40, the insulating film 41,and the p⁻ type epitaxial layer 42 is constructed.

[0085] [Step shown in FIG. 7B]

[0086] Next, after a mask having an opening where the n⁻ type driftregion 1 c is to be formed is formed in a photostep, etching isperformed using the mask to form a trench 45. At that time, the dryetching similar to that in the step shown in FIG. 1B is performed toetch the p⁻ type epitaxial layer 42 and the n⁺ type substrate 40, andeither of dry etching and wet etching using HF or the like is performedto etch the insulating film 41. Then, the mask is removed.

[0087] Incidentally, wet etching may be performed to etch the p⁻ typeepitaxial layer 42 and the n⁺ type substrate 40, instead of the dryetching as in the fifth embodiment. Likewise, the aspect ratio of thetrench 45 can be increased by using the (110) Si substrate as the n⁺type substrate 40, and by so designing that the sidewalls of the trench45 are defined by a (1{overscore (1)}1) plane and a ({overscore(1)}1{overscore (1)}) plane, or by a ({overscore (1)}11) plane and a(1{overscore (11)}) plane.

[0088] [Step shown in FIG. 7C]

[0089] Next, an n⁺ type epitaxial film 43 is deposited, so that thesidewalls of the trench 45 are covered with the n⁺ type epitaxial film43. The n⁺ type epitaxial film 43 and the n⁺ type substrate 40 work asthe drain (corresponding to the n⁺ type substrate 1 in the firstembodiment) of the power MOSFET. Then, substantially the same steps asthose shown in FIG. 2B and following it are performed. As a result, then⁻ type drift region 1, the p type base region 2, an the n⁺ type sourceregion 3 are provided.

[0090] Thus, even in the case where the semiconductor device isfabricated by using the SOI substrate as above, since the p⁻ typeepitaxial layer 42 is disposed at the peripheral device formationregion, the same advantages as in the fifth embodiment can be attained.Incidentally, in the case of using the SOI substrate, respective devicesformed in the SOI substrate are electrically isolated from one anotherby an insulating film 44. In this connection, when the power MOSFET issurrounded with this insulating film 44, the electrical isolation can beattained more securely.

[0091] In the first to fifth embodiments as described above, because theperipheral device and the power MOSFET are isolated from each other, aspecial step for obtaining the device isolation is not performed.However, a LOCOS isolation or STI (Shallow Trench Isolation) may beperformed to make the device isolation more secure.

[0092] In each of the embodiments, the three-layered structure composedof the n⁻ type drift region 1 c, the p type base region 2, and the n⁺type source region 3 is formed by depositing the three epitaxial films22 to 24; however, it may be formed as follows. For example, the n⁻ typeepitaxial film 22 is formed to have a larger thickness, and a p typefilm containing p type impurities is deposited on the surface of the n⁻type epitaxial film 22. The surface portion of the n⁻ type epitaxialfilm 22 is then inverted into a p type by solid phase diffusion from thep type film so that the p type base region 2 is formed. Instead of solidphase diffusion, p type impurities may be diffused into the n⁻ typeepitaxial film 22 at a gaseous phase or a liquid phase.

[0093] (Seventh Embodiment)

[0094] Next, a seventh embodiment of the present invention is explained.In this and following embodiments, a peripheral device has a structuresimilar to that of a power MOSFET, and therefore, can be manufactured atthe same manufacturing steps as those for the power MOSFET on anidentical substrate.

[0095]FIG. 16 shows the power MOSFET adopted in this embodiment. Thepower MOSFET has a structure substantially the same as that shown inFIG. 8 except that the trenches 5 do not penetrate the p type baseregion 2 in the direction X (the trenches 5 have end portions in the ptype base region 2), and that high-concentration contact regions 108,109 are provided. The high-concentration contact regions 108, 109 extendin the p type base region 2 and the n⁺ type substrate 1, respectively,from the main surface 1 a in a vertical direction (depth direction) sothat internal resistances of the p type base region 2 and the n⁺ typesubstrate 1 are reduced in the depth direction.

[0096] Next, the semiconductor device including the power MOSFET and theperipheral device according to the seventh embodiment is explained withreference to FIG. 9, in which the same parts as those in FIG. 16 aredesignated with the same reference numerals.

[0097] The semiconductor device has power MOSFETs and peripheral devicesthat are formed on an identical n⁺ type substrate 1. The power MOSFETsare formed at region (power MOSFET formation region) A of the n⁺ typesubstrate 1, and the peripheral devices are formed at region (peripheraldevice formation region) B thereof.

[0098]FIG. 16 corresponds to a cross-section taken along lines XVI-O-XVIin FIG. 9, and each of the power MOSFETs provided continuously at thepower MOSFET formation region A has the structure shown in FIG. 16. Atthe peripheral device formation region B, n-channel MOSFETs are formedas peripheral devices for, for example, controlling the power MOSFETs.FIG. 10 shows a cross-section taken along lines X-O-X in FIG. 9. Thestructure of one of the n-channel MOSFETs as a peripheral device isexplained below based on this figure.

[0099] This MOSFET as well as the power MOSFET is formed on the n⁺ typesubstrate 1 having the main surface 1 a and the back surface 1 b.Arrowed direction X corresponds to the thickness direction of the n⁺type substrate 1, and arrowed directions Y and Z correspond todirections parallel to the main surface 1 a and the back surface 1 b ofthe n⁺ type substrate 1. The directions X, Y, and Z are perpendicular toone another.

[0100] An n⁻ well layer 111 is formed with a specific depth from themain surface 1 a of the n⁺ type substrate 1, and a p type base region112 is formed in the n⁻ type well layer 111 to have a specific depthfrom the main surface 1 a of the n⁺ type substrate 1. The depth of the ptype base region 112 is about 1 to 100 μm. An n⁺ type region 13 isfurther formed in the p type base region 112 from the main surface 1 aof the n⁺ type substrate 1 to have a junction depth shallower than thatof the p type base region 112. The depth of the n⁺ type region 13 isabout 1 to 100 μm, but is somewhat shallower than that of the p typebase region 112.

[0101] Trenches 14, 15 are dug from the main surface 1 a of the n⁺ typesubstrate 1 perpendicularly, i.e., in parallel with the direction X. Thetrench 14 extends in the direction Y parallel to the main surface 1 a toreach the p type base region 112 while passing through the n⁺ typeregion 13, and extends in the direction X parallel to the depthdirection thereof to pass through the n⁺ type region 13 and to reach thep type base region 112. As a result, the n⁺ type region 13 is divided,in the direction Z, into a source region 13 a and a drain region 13 b.Further, a gate oxide film (gate insulating film) 16 is formed on thesurface of the trench 14, and a gate electrode 17 made of poly siliconis embedded inside the trench 14 through the gate oxide film 16.

[0102] On the other hand, the trench (isolation trench) 15 is formed topenetrate both the n⁺ type region 13 and the p type base region 112 inthe direction Y parallel to the main surface 1 a of the n⁺ typesubstrate 1. In the direction X parallel to the depth direction of thetrench 15, the trench 15 penetrates the n⁺ type region 13 to reach the ptype base region 112. An oxide film (isolation insulating film) 18 isformed on the surface of the trench 15, and the inside of the trench 15is filled with a poly-silicon layer 19 with the oxide film 18interposed. As shown in FIG. 9, although the MOSFETs are providedcontinuously, the respective MOSFETs are isolated from each other by thetrench 15 and the oxide film 18. Incidentally, a high-concentrationcontact region 120 is provided in the p type base region 112, whichextends perpendicularly from the main surface 1 a so that the internalresistance of the p type base region 112 is reduced in the depthdirection.

[0103] The above-mentioned MOSFET is operated as follows.

[0104] Referring to FIG. 11 showing an operational state of the MOSFET,because the trench 14 passes through the n⁺ type region 13, a channelregion is formed to surround the protruding portions protruding from then⁺ type region 13. Accordingly, a current flows between the sourceregion and the drain region when a driving voltage is applied to thegate electrode 17.

[0105] Thus, when the peripheral device formed on the same substrate asthe power MOSFET has the above-mentioned structure similar to that ofthe power MOSFET, the power MOSFET and the peripheral device can beproduced at the same manufacturing steps.

[0106] Next, after the manufacturing steps for the power MOSFET areexplained, the method for manufacturing the semiconductor device isexplained in comparison with the manufacturing steps for the powerMOSFET and the manufacturing steps for the peripheral device. Themanufacturing steps for the power MOSFET are explained with reference toFIG. 16.

[0107] The manufacture of the power MOSFET shown in FIG. 16 is, forexample, performed as follows. First, the trench is formed on the n⁺type substrate 1 where the n⁻ type drift region 1 c is to be formed.Then, three layers composed of an n⁻ type epitaxial film, a p typeepitaxial film, and an n⁺ type epitaxial film are deposited on the mainsurface 1 a of the n⁺ type substrate 1 including the trench, and thesurface of the three layers is flattened. Accordingly, the n⁻ type driftregion 1 c, the p type base region 2, and the n⁺ type source region 3are provided. Successively, after the trenches 5 are formed, the innerwalls of the trenches 5 are thermally oxidized to form the gate oxidefilm 6. On the gate oxide film 6, a poly silicon layer is deposited toform the gate electrode 7. The contact regions 108, 109 are formed byion-implantation performed through the main surface 1 a. In consequence,the power MOSFET is completed.

[0108] The manufacturing steps for the peripheral device can beperformed simultaneously with the above-mentioned manufacturing stepsfor the power MOSFET as follows.

[0109] First, when the trench is formed where the n⁻ type drift region 1c is formed, a trench is also formed at a region where the n⁻ type wellregion 111 is to be formed. Then, the three epitaxial films aredeposited to fill both the trenches, and the flattening step describedabove is performed. Accordingly, the n⁻ type well layer 111, the p typebase region 112, and the n⁺ type region 13 can be formed simultaneouslyat the steps for forming the n⁻ type drift region 1 c, the p type baseregion 2, and the n⁺ type source region 3.

[0110] Further, the trenches 14, 15 are formed simultaneously when thetrenches 5 are formed. The gate oxide film 16 and the oxide film 18 areformed during the thermal oxidation for forming the gate oxide film 6.The gate electrode 17 and the poly silicon layer 19 are formedsimultaneously when the gate electrode 7 is formed. Thus, the trenches 5and the trenches 14, 15 can be formed at the same step, the gate oxidefilm 6, the gate oxide film 16, and the oxide film 18 can be formed atthe same step, and the gate electrode 7, the gate electrode 17, and thepoly silicon layer 19 can be formed at the same step.

[0111] Because the power MOSFET and the peripheral device can bemanufactured at the same steps, the manufacturing method of thesemiconductor device can be simplified. Incidentally, although themanufacturing method of the semiconductor device is exemplified asabove, it may be modified appropriately provided that each step can beperformed for forming both the power MOSFET and the peripheral device.

[0112] (Eighth Embodiment)

[0113]FIG. 12 shows a semiconductor device to which an eighth embodimentof the invention is applied. In the seventh embodiment, the n-channelMOSFET is formed as a peripheral device; however, in this embodiment, aCMOS including not only an n-channel MOSFET (nMOS) but also a p-channelMOSFET (PMOS) is formed as a peripheral device. The n-channel MOSFET hasa structure substantially the same as that explained in the seventhembodiment. Therefore, the p-channel MOSFET is mainly explained below.

[0114] As shown in FIG. 12, a trench 131 is formed in the n⁻ type wellregion 111 to extend perpendicularly to the main surface 1 a. A gateoxide film 132 is formed on the inner wall of the trench 131, and a gateelectrode 133 made of poly silicon is embedded in the trench 131 withthe gate oxide film 132 interposed therebetween.

[0115] A p type source region 134 and a p type drain region 135 areprovided in the n⁻ type well layer 111 in contact with the side face ofthe trench 131. Each of the p type source region 134 and the p typedrain region 135 extends from the main surface 1 a in the direction Xwith a depth and an impurity concentration which are approximately equalto those of the contact region 120. In the p-channel MOSFET having theabove-mentioned structure, as shown in FIG. 13, a channel region isformed along the side face of the trench 131 so that current flowsbetween the source region and the drain region when a driving voltage isapplied to the gate electrode 133.

[0116] When the CMOS is constructed as above, the power MOSFET and theperipheral device can be formed at the same manufacturing steps evenwhen the peripheral device is formed on the identical substrate with thepower MOSFET. For example, when the trenches 5 of the power MOSFET areformed, the trenches 14, 15 of the n-channel MOSFET and the trench 131of the p-channel MOSFET are formed simultaneously. During the thermaloxidation for forming the gate oxide film 6 of the power MOSFET, thegate oxide film 16 and the oxide film 18 of the n-channel MOSFET, andthe gate oxide film 132 of the p-channel MOSFET are formedsimultaneously. Successively, when the gate electrode 7 of the powerMOSFET is formed, the gate electrode 17 and the poly silicon layer 19 ofthe n-channel MOSFET and the gate electrode 133 of the p-channel MOSFETare formed simultaneously. Thus, the power MOSFET and the CMOS can beformed at the same manufacturing steps, resulting in simplifiedmanufacturing method of the semiconductor device.

[0117] In the eighth embodiment, the p type source region 134 and the ptype drain region 135 are disposed at one side of the trench 131;however, as shown in FIG. 14, they may be disposed at both sides of thetrench 131. In this case, because the channel region is formed along theboth side faces of the trench 131, the channel width is increased twicesubstantially. This results in reduced channel resistance.

[0118] Also, as shown in FIG. 15, the p type source region 134 and the ptype drain region 135 may be provided to surround both end portions ofthe trench 131 in the longitudinal direction of the trench 131. In thiscase, likewise, the channel region is formed along the both side facesof the trench 131, so that the same advantages as described above can beattained. Incidentally, in the embodiments described above, although thedrain region is composed of the n⁺ type substrate 1, the drain regionmay be composed of a region extending from the main surface 1 a in thedirection perpendicular to the main surface 1 a. In the respectiveembodiments, the conductive types of the p type and the n type may beinversed to each other. In this case, in the structure of the seventhembodiment, a p-channel MOSFET is formed as a peripheral device. In thestructure of the eighth embodiment, the positions of the p-channelMOSFET and the n-channel MOSFET in the CMOS are inversed to each otherwith respect to those shown in FIG. 12.

[0119] While the present invention has been shown and described withreference to the foregoing preferred embodiments, it will be apparent tothose skilled in the art that changes in form and detail may be madetherein without departing from the scope of the invention as defined inthe appended claims.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate of a first conductivity type having a mainsurface that includes a power MOSFET formation region having a firsttrench for forming a power MOSFET thereon and a peripheral deviceformation region having a second trench for forming a peripheral devicethereon, the semiconductor substrate surrounding the first trench beingfor working as a drain of the power MOSFET; and a well layer of a secondconductivity type disposed in the second trench of the peripheral deviceformation region.
 2. The semiconductor device according to claim 1 ,wherein: the power MOSFET comprises; a drift region of the firstconductivity type, disposed in the first trench and having an impurityconcentration lower than that of the semiconductor substrate; a baseregion of the second conductivity type, disposed in the drift region andextending from the main surface in a perpendicular direction withrespect to to the main surface; a source region of the firstconductivity type, disposed in the base region and extending from themain surface in the perpendicular direction; a gate insulating filmdisposed on a surface of a third trench that extends from the mainsurface in the perpendicular direction and penetrates the source regionand the base region; and a gate electrode disposed on the gateinsulating film and filling the third trench; and the peripheral devicecomprises; a semiconductor layer of the first conductivity type havingan impurity concentration lower than that of the semiconductorsubstrate, and disposed in the second trench; and the well layerdisposed in the semiconductor layer.
 3. The semiconductor deviceaccording to claim 2 , wherein the second trench has a depth that isequal to or less than a thickness of the drift region.
 4. Thesemiconductor device according to claim 2 , wherein the second trenchhas a width that is twice or less than twice as large as a thickness ofthe drift region.
 5. The semiconductor device according to claim 2 ,wherein the second trench has a depth that is equal to or less than asum of a thickness of the drift region and a thickness of the baseregion.
 6. The semiconductor device according to claim 2 , wherein thesecond trench has a width that is equal to or less than twice as largeas a sum of a thickness of the drift region and a thickness of the baseregion.
 7. A semiconductor device comprising: a semiconductor substrateof a first conductivity type; a semiconductor layer of a secondconductivity type disposed on a surface of the semiconductor substrateand having a main surface at an opposite side of the semiconductorsubstrate; a power MOSFET formed in a first trench that extends from themain surface of the semiconductor layer, penetrates the semiconductorlayer, and reaches the semiconductor substrate, the power MOSFETcomprising: a drift region of the first conductivity type disposed inthe first trench and having an impurity concentration lower than that ofthe semiconductor substrate; a base region of the second conductivitytype formed in the drift region and extending from the main surface in aperpendicular direction with respect to the main surface; a sourceregion of the first conductivity type formed in the base region andextending from the main surface in the perpendicular direction; a gateinsulating film disposed on a surface of a second trench that extendsfrom the main surface in the perpendicular direction and penetrates thesource region and the base region; and a gate electrode disposed on thegate insulating film and filling the second trench; and a peripheraldevice provided in the semiconductor layer at a region different from aregion where the power MOSFET is provided.
 8. The semiconductor deviceaccording to claim 7 , further comprising an insulating film disposedbetween the semiconductor substrate and the semiconductor layer.
 9. Amethod for manufacturing a semiconductor device, comprising: preparing asemiconductor substrate of a first conductivity type having a main surface that has a power MOSFET formation region for forming a power MOSFETand a peripheral device formation region for forming a peripheraldevice; forming a first trench at the power MOSFET formation region onthe semiconductor substrate; forming a second trench at the peripheraldevice formation region on the semiconductor substrate; forming a firstsemiconductor film of the first conductivity type on the main surfaceand on sidewalls of the first and second trenches, the firstsemiconductor film having an impurity concentration lower than that ofthe semiconductor substrate; forming a second semiconductor film of asecond conductivity type on the first semiconductor film; forming athird semiconductor film of the first conductivity type on the secondsemiconductor film, the third semiconductor film having an impurityconcentration higher than that of the first semiconductor film; andflattening a surface of the first to third semiconductor films forming athree-layered structure, wherein: the first trench is sized so that allof the first to third semiconductor films are disposed in the firsttrench to form the power MOSFET in which the first semiconductor filmconstitutes a drift region, the second semiconductor film constitutes abase region, and the third semiconductor film constitutes a sourceregion; and the second trench is sized so that at least the firstsemiconductor film is disposed in the second trench.
 10. The methodaccording to claim 9 , wherein the second trench is formed at a depththat is equal to or less than a thickness of the first semiconductorfilm.
 11. The method according to claim 9 , wherein: the first trenchand the second trench are formed simultaneously; the second trench isformed with a width that is twice or less than twice as large as athickness of the first semiconductor film.
 12. The method according toclaim 9 , wherein: the first trench and the second trench are formedsimultaneously; the second trench is formed at a depth that is equal toor less than a sum of a thickness of the first semiconductor film and athickness of the second semiconductor film.
 13. The method according toclaim 9 , wherein: the first trench and the second trench are formedsimultaneously; the second trench is formed with a width that is twiceor less than twice as large as a sum of a thickness of the firstsemiconductor film and a thickness of the second semiconductor film. 14.The method according to claim 9 , wherein the first to thirdsemiconductor films are epitaxially grown.
 15. The method according toclaim 9 , wherein: the first semiconductor film is formed by anepitaxial growth; the second semiconductor film is formed by invertingthe conductivity type of a surface portion of the first semiconductorfilm from the first conductivity type into the second conductivity type;and the third semiconductor film is formed on the second semiconductorfilm by the epitaxial growth.
 16. A method for manufacturing asemiconductor device, comprising: preparing a semiconductor substrate ofa first conductivity type having thereon a semiconductor layer of asecond conductivity type; forming a trench from a surface of thesemiconductor layer in a perpendicular direction with respect to thesurface so that the trench reaches the semiconductor substrate; forminga first semiconductor film of the first conductivity type on the surfaceof the semiconductor layer and on a sidewall of the trench, the firstsemiconductor film having an impurity concentration lower than that ofthe semiconductor substrate; forming a second semiconductor film of thesecond conductivity type on the first semiconductor film; forming athird semiconductor film of the first conductivity type on the secondsemiconductor film, the third semiconductor film having an impurityconcentration higher than that of the first semiconductor film; andflattening a surface of the first to third semiconductor films forming athree-layered structure, wherein: the trench is sized so that all of thefirst to third semiconductor films are disposed in the trench to form apower MOSFET in which the first semiconductor film constitutes a driftregion, the second semiconductor film constitutes a base region, and thethird semiconductor film constitutes a source region; and a peripheraldevice is formed in the semiconductor layer except a region where thepower MOSFET is provided.
 17. The method according to claim 16 , whereinthe semiconductor layer is disposed on the semiconductor substrate withan insulating layer interposed therebetween.
 18. The method according toclaim 16 , further comprising, forming a fourth semiconductor film onthe sidewall of the trench before the first semiconductor film isformed, the forth semiconductor film having an impurity concentrationhigher than that of the first semiconductor film.
 19. The methodaccording to claim 16 , wherein the first to third semiconductor filmsare epitaxially grown.
 20. The method according to claim 16 , wherein:the first semiconductor film is formed by an epitaxial growth; thesecond semiconductor film is formed by inverting the conductivity typeof a surface portion of the first semiconductor film from the firstconductivity type into the second conductivity type; and the thirdsemiconductor film is formed on the second semiconductor film by theepitaxial growth.
 21. A semiconductor device comprising: a firstconductivity type semiconductor substrate; a power MOSFET formed in thesemiconductor substrate at a power MOSFET formation region, the powerMOSFET including a drain that is composed of the semiconductorsubstrate; a peripheral device formed in the semiconductor substrate ata peripheral device formation region; and a semiconductor regionsurrounding the peripheral device to separate the peripheral device fromthe semiconductor substrate, and having an impurity concentration lowerthan that of the semiconductor substrate.
 22. The semiconductor deviceaccording to claim 21 , wherein the semiconductor region is provided ina trench provided in the semiconductor substrate at the peripheraldevice formation region.
 23. The semiconductor device according to claim22 , wherein the semiconductor region is composed of a firstconductivity type semiconductor region having an impurity concentrationlower than that of the semiconductor substrate and disposed on an innerwall of the trench, and a second conductivity type semiconductor wellregion provided in a surface portion of the first conductivity typesemiconductor region.
 24. The semiconductor device according to claim 21, wherein: the power MOSFET is provided in a first trench of thesemiconductor substrate; the semiconductor region in which theperipheral device is provided is provided in a second trench of thesemiconductor substrate, the second trench being different from thefirst trench in size.
 25. The semiconductor device according to claim 24, wherein at least one of a width and a depth of the second trench issmaller than that of the first trench.
 26. The semiconductor deviceaccording to claim 21 , wherein; the semiconductor region is disposed ona surface of the semiconductor substrate; the power MOSFET is providedin a trench extending from a surface of the semiconductor region andpenetrating the semiconductor region to reach the semiconductorsubstrate that works as the drain of the power MOSFET; and theperipheral device is formed in the semiconductor region apart from thetrench.
 27. The semiconductor device according to claim 26 , wherein thesemiconductor region has a second conductivity type.
 28. Thesemiconductor device according to claim 26 , further comprising aninsulating film interposed between the semiconductor substrate and thesemiconductor region, wherein: the trench penetrates the semiconductorregion and the insulating film to reach the semiconductor substrate. 29.A semiconductor device comprising: a semiconductor substrate of a firstconductivity type, having a main surface and a back surface; a powerMOSFET formed in the semiconductor substrate; and a peripheral deviceformed in the semiconductor substrate, wherein the power MOSFETcomprises: a drift region of the first conductivity type extending inthe semiconductor substrate from the main surface in a perpendiculardirection with respect to the main surface; a base region of a secondconductivity type extending in the drift region from the main surface inthe perpendicular direction; a source region of the first conductivitytype extending in the base region from the main surface in theperpendicular direction; a trench extending from the main surface in theperpendicular direction, and penetrating the base region from the sourceregion to the drift region; a gate insulating film provided on an innerwall of the trench; and a gate electrode provided on a surface of thegate insulating film and filling an inside of the trench, and whereinthe peripheral device is a first conductivity type channel MOSFET, andcomprises: a well layer of the first conductivity type extending in thesemiconductor substrate from the main surface in the perpendiculardirection; a base region of the second conductivity type extending inthe well layer from the main surface in the perpendicular direction; asemiconductor region of the first conductivity type extending in thebase region from the main surface in the perpendicular direction; atrench extending from the main surface in the perpendicular directionand dividing the semiconductor region into a source region and a drainregion; a gate insulating film provided on an inner wall of the trench;and a gate electrode provided on a surface of the gate insulating filmand filling an inside of the trench.
 30. The semiconductor deviceaccording to claim 29 , wherein the semiconductor device is manufacturedby: forming the drift region of the power MOSFET and the well layer ofthe peripheral device simultaneously; forming the base region of thepower MOSFET and the base region of the peripheral devicesimultaneously; forming the source region of the power MOSFET and thesemiconductor region of the peripheral device simultaneously; formingthe trench of the power MOSFET and the trench of the peripheral devicesimultaneously; forming the gate insulating film of the power MOSFET andthe gate insulating film of the peripheral device simultaneously; andforming the gate electrode of the power MOSFET and the gate electrode ofthe peripheral device simultaneously.
 31. The semiconductor deviceaccording to claim 29 , further comprising first and second peripheraldevices each of which is the first conductivity type channel MOSFETcomprising the well layer, the base region, the semiconductor regiondivided into the source region and the drain region by the trench, thegate insulating film and the gate electrode, wherein: the base region ofthe first peripheral device and the base region of the second peripheraldevice are electrically separated from each other by an isolation trenchextending from the main surface in the perpendicular direction, aninsulating film provided on an inner wall of the isolation trench, and apoly silicon layer provided on a surface of the isolation insulatingfilm and filling the isolation trench.
 32. The semiconductor deviceaccording to claim 31 , wherein the semiconductor device is manufacturedby; forming the trench of each of the first and second peripheraldevices and the isolation trench simultaneously; forming the gateinsulating film of each of the first and second peripheral devices andthe isolation insulating film simultaneously; and forming the gateelectrode of each of the first and second peripheral devices and thepoly silicon layer simultaneously.
 33. The semiconductor deviceaccording to claim 29 , wherein the peripheral device further includes asecond conductivity type channel MOSFET comprising: a trench extendingin the well layer from the main surface in the perpendicular direction;a gate insulating film provided on an inner wall of the trench; a gateelectrode provided on a surface of the gate insulating film and fillingthe trench; a source region of the second conductivity type extending inthe well layer from the main surface in contact with the gate insulatingfilm at a side of the trench; and a drain region of the secondconductivity type extending in the well layer from the main surface incontact with the gate insulating film at the side of the trench, thedrain being separated from the source region.
 34. The semiconductordevice according to claim 33 , wherein the source region and the drainregion of the second conductivity type channel MOSFET are provided atboth sides of the trench thereof.
 35. The semiconductor device accordingto claim 33 , wherein, in the second conductivity type channel MOSFET,the source region surrounds a first end portion of the trench, and thedrain region surrounds a second end portion of the trench opposite tothe first end portion in a direction parallel to the main surface of thesemiconductor substrate.
 36. The semiconductor device according to claim29 , the power MOSFET further includes a high-concentration contactregion of the second conductivity type extending in the base region fromthe main surface in the perpendicular direction and having an impurityconcentration higher than that of the base region.
 37. A semiconductordevice comprising: a semiconductor substrate of a first conductivitytype, having a main surface and a back surface; a power MOSFET formed inthe semiconductor substrate; and a peripheral device formed in thesemiconductor substrate, wherein the power MOSFET comprises: a driftregion of the first conductivity type extending in the semiconductorsubstrate from the main surface in a perpendicular direction withrespect to the main surface; a base region of a second conductivity typeextending in the drift region from the main surface in the perpendiculardirection; a source region of the first conductivity type extending inthe base region from the main surface in the perpendicular direction; atrench extending from the main surface in the perpendicular direction,and penetrating the base region from the source region to the driftregion; a gate insulating film provided on an inner wall of the trench;and a gate electrode provided on a surface of the gate insulating filmand filling an inside of the trench, and wherein the peripheral deviceis a second conductivity type channel MOSFET, and comprises: a welllayer of the first conductivity type extending in the semiconductorsubstrate from the main surface in the perpendicular direction, andhaving an impurity concentration lower than that of the semiconductorsubstrate; a trench extending in the well layer from the main surface inthe perpendicular direction; a gate insulating film provided on an innerwall of the trench; a gate electrode provided on a surface of the gateinsulating film and filling the trench; a source region of the secondconductivity type extending in the well layer from the main surface incontact with the gate insulating film at a side of the trench; and adrain region of the second conductivity type extending in the well layerfrom the main surface in contact with the gate insulating film at theside of the trench, the drain region being separated from the sourceregion.
 38. The semiconductor device according to claim 37 , wherein thepower MOSFET further comprises a high-concentration contact region ofthe second conductivity type extending in the base region from the mainsurface in the perpendicular direction and having an impurityconcentration higher than that of the base region.
 39. The semiconductordevice according to claim 38 , manufactured by: forming the drift regionof the power MOSFET and the well layer of the peripheral devicesimultaneously; forming the high-concentration contact region of thepower MOSFET and the source region and the drain region of theperipheral device simultaneously; forming the trench of the power MOSFETand the trench of the peripheral device simultaneously; forming the gateinsulating film of the power MOSFET and the gate insulating film of theperipheral device simultaneously; and forming the gate electrode of thepower MOSFET and the gate electrode of the peripheral devicesimultaneously.
 40. The semiconductor device according to claim 37 ,wherein the source region and the drain region of the secondconductivity type channel MOSFET are provided at both sides of thetrench thereof.
 41. The semiconductor device according to claim 37 ,wherein, in the second conductivity type channel MOSFET, the sourceregion surrounds a first end portion of the trench, and the drain regionsurrounds a second end portion of the trench opposite to the first endportion in a direction parallel to the main surface of the semiconductorsubstrate.
 42. A semiconductor device comprising: a semiconductorsubstrate of a first conductivity type and having a main surface with afirst area where a power MOSFET is provided and a second area where aperipheral device is provided; first and second semiconductor regions ofthe first conductivity type, respectively provided in the semiconductorsubstrate at the first area and the second area and having impurityconcentrations approximately equal to each other and lower than that ofthe semiconductor substrate; first and second trenches respectivelyextending in the first and second semiconductor regions and havingdepths approximately equal to each other; first and second insulatingfilms respectively provided on inner walls of the first and secondtrenches; and first and second conductive members respectively fillingthe first and second trenches with the first and second insulating filmsinterposed therebetween, wherein: the power MOSFET is composed of thefirst semiconductor region as a drift region, a base region of a secondconductivity type extending in the drift region, a source region of thefirst conductivity type extending in the base region, the firstinsulating film as a gate insulating film, and the first conductivemember as a gate electrode that extends to face the drift region, thebase region, and the source region via the gate insulating layer; andthe peripheral device is a MOSFET composed of the second semiconductorregion as a well layer, the second insulating film as a gate insulatingfilm, the second conductive member as a gate electrode, source and drainregions provided in the well layer separately from each other, thesource and drain regions facing the gate electrode with the gateelectrode interposed therebetween.
 43. The semiconductor deviceaccording to claim 42 , wherein: the peripheral device is a firstconductivity type channel MOSFET, and further includes a base region ofthe second conductivity type having a depth approximately equal to thatof the base region of the power MOSFET; and the source and drain regionsof the peripheral device are of the first conductivity type and have adepth approximately equal to that of the source region of the powerMOSFET.
 43. The semiconductor device according to claim 42 , wherein:the peripheral device is a second conductivity type channel MOSFET; andthe source and drain regions of the peripheral device are of the secondconductivity type.